Welcome to Ver Structural Verilog Compiler v0.98! I created this because I saw a need for a small portable Verilog compiler that doesn't have the sourcecode size limits of the VeriWell training simulator. Note that this is a *structural* compiler. Behaviorals (initial/always) are not supported in the compiler's parser yet. It's planned, but I don't know when I'll get around to writing that part. I'm tossing around the possibility of *not* including it and going the "add on module" route instead (i.e., using C programs that interface with the simulator). It's much faster and it's probably the way to go since the cycle simulator compiler (Cyco) generates C code anyway.

Look in the "examples" directory to get an idea of what the compiler can do. Any peculiarities in syntax will be noted in comment lines in the sourcecode. For the most part, any minor limitations will be noted in comment blocks in the sourcecode. I still have to work on making the parser a little more flexible like allowing parameters and things like that. I'm officially done working on this project for a little while--at least until I get accustomed to taking grad classes. (Compilers *shrug*, it figures..)

The event simulator bundled with this is from the VHDL simulator VSIM from the University of Pittsburgh. As its authors say:

	This software is distributed on an as-is basis with no
	warranty implied or intended.  No author or distributor
	takes responsibility to anyone regarding its use of or
	suitability. 

	The software may be distributed and modified freely for
	academic and other non-commercial use but may NOT be
	utilized or included in whole or part within any
	commercial product. 

As far as the ver directory goes, you can do with it whatever you feel like. But if you do anything interesting, please let me know.

An instruction manual will be coming probably in the next release (both FrameMaker doc files and Postscript PS ones), but for the time being, here are some random odds and ends to get you started:

** Ver takes its input from stdin unless otherwise directed (or UNODIR as Navy Seal extraordinaire Dick Marcinko says). To use the compiler on text files you can do one of two things:

	ver <filename	or
	ver filename

** Ver will "flatten" your design out and not include unused modules in the flattened (.ivf) file. However, the algorithm used to determine the topmost module requires that the module has to instantiate at least one component inside of it (and the module itself isn't instantiated elsewhere). If this doesn't find your module or you want to flatten from a different one, use the -f flag. (ver -h will show you the other compile flags.)

** No signals are optimized out. You have to run the .ivf file through Cyco with the -w flag if you want an optimized .ivf model. Of course an unoptimized model causes some very long signal names, but the positive side of this is that you can use two signal names to refer to the same signal. (You can see both sides of a bus, wire, etc.) The down side of this is that simulation time increases since VSIM has to keep track of more nodes. As indicated elsewhere in this document, canned storage elements are provided for cycle simulation to alleviate this problem.

** If long simulation times are an issue with larger models, use Cyco with no options to generate a C code model. It's your responsibility to multiplex facilities (signals) into and out of the model.

** It is not difficult to convert Ver so it writes out BDNET format files for logic synthesis. The ability to write out either flattened or hierarchical designs with fanin/out testing may be in a future version of Ver. It depends on how motivated I get with this project. =) Cyco does accurate fan counts now (assuming you run a -w optimized .ivf model through it), so a future version should be able to calculate capacitive loading effects and such when standard cell technology libraries (forthcoming) are supplied.

** CONSTX and CONSTZ gates will compile but the cycle simulator cannot handle them. Multilevel logic isn't handled in Cyco yet since that would double the runtime of a model. (The X/Z part has to be calculated as well in a "stacked" logic definition: 0=%00, 1=%01, X=%10, Z=%11.)

** VSIM has been mutilated. It now handles 0, 1, X, Z logic.

** When compiling VSIM, if your compiler doesn't find the ftime() function (it's in libcompat on my Amiga running NetBSD; your location may be different), do a "man ftime" to find out where you have to point the Makefile in VSIM to link it in. (i.e., -lbsd, -lcompat, etc.)

** Assertions, etc. would probably be nice in VSIM. Also, restarting simulation from any arbitrary point in an aet could prove useful. (You can "back out" of a simulation and go down a different path this way.) It's hard to say what I would like to add to VSIM since I'm concentrating on Cyco at this point.

** To view aet's, run anna on the .aet and .wav (optional) files for your design. Look in the examples directory to see how to do this. Also, invoking anna without command line arguments will give you the command usage.

** Compiling anna on PPC AIX boxes requires you to "tell" the compiler that it is SYS_V. (The signal() function never gets called otherwise.)

** mem.c in anna uses etext(). This is missing under AIX. Use the MIPS patch shown in the mem.c code instead.

** Faaast cycle simulation has been realized with Cyco, the cycle compiler. IVF files can be compiled into C code! I've kept VSIM since Cyco chucks away all timing information and uses strict combinational circuits (detecting data dependencies and sorting the generated c code as necessary). Tracing is still NP hard, but searching from outputs->inputs speeds things up a lot. Cyco can convert the package.ivf (700 gates) into a .c file in 18 seconds. If you convert a -w optimized model, package.ivf drops down to a 4 second conversion.

In examples/lines-cyco, you'll find an example of how to use Cyco. It generates an x-windows front end so you can see what's going on. If you're running in 16 million colors, doom on you..it isn't going to work.

** Use Gen for numeric macro expansion for repetitive signal instances, declarations, etc. Look at the test* files in the gen directory to see what it can do. A couple of files do things like figure out GCD's, etc. It's quite fast too since the "interpreting" is a nothing more than a recursive syntax treewalk on the tree of structs the parser creates. (See gen/exec.c to see what I mean.)

** In the future I'll add combinational circuit extraction to Cyco so that tools like espresso/misII/sis (or a mapper supplied with a future version of Ver) can be run on the chunks for technology mapping and synthesis. The extraction isn't hard--there's just a lot going on in this project and it's not my top priority!

** Quine-McCluskey is being worked on (I have the prime implicant, essential PI routines working but have to do maximal irredundant cover) for truth table directive expansion and such in Gen. Depending on how the espressoII coding goes, QM may never see the light of day in a Ver release. I've been putting it off for a while and working on Ver's parser instead.

Well, that's about it for now. 1.0 should be the next "major" update with these 0.1 revs in between. Have fun!

25jan98 bybell@buster.nac.net / bybell@xxedgexx.com / bybell@vnet.ibm.com

Change Log:
-----------

24/08/97	Added support for aet generation in vsim.
26/08/97	Made component instantiations with duplicate names illegal.
27/08/97	Fixed flatten.c so it outputs UNK as the gate type if 
			there are unspecified input/output ports.
27/08/97	Updated symbol.c to give the user a warning in UNK
			gates are present (i.e., IP+OP!=TP).
27/08/97	Started work on an ivf network analyzer (Mizer).
31/08/97	Fixed assign statements so a statement like 
			assign #(2,2) o=(a&b)|c; gives a zero delay for
			the (a&b)|c operation and a (2,2) for the 
			temporary wire connecting the gates to "o".
07/09/97	Started work on adapting the irsim graphical front end
			to view vsim generated aet's.
11/09/97	aet's are viewable in anna.  Useful features such as search
			have yet to be implemented.
15/09/97	Added single bit searching (0, 1, X, upclock, downclock) 
			functions to the search menu.
18/09/97	Added bit vector searching routines, but only for fixed
			values..have to add bin, oct, hex input routines
			yet.  Also fixed searches so they update the 
			values column along the right side of the window
			and the trace cache as they should.
20/09/97	Search input routines done.  Also changed anna to reject
			aet's of zero duration.
01/10/97	Added edge triggered D flip-flops to ver in format of
			latch(q,d).  Clocking is under the control of the sim.  
			Also fixed bug where xnor gate numbers in the
			ivf file don't increment.  (misplaced break stmt.)
04/10/97	Updated mizer to do output/latch -> input/prev latch
			traversals.  Fast loop detections are now 
			possible and the starting of a c-code generator
			for cycle-simulation is working.  Timing 
			information is thrown away as the goal is a
			*fast* cycle simulation.  Also, it only
			supports two-level logic at this point.  (no "X")
07/10/97	Renamed mizer to "Cyco" (pronounced psycho).  Parallel
			simulation of identical models is possible
			with the c code generated by cyco.  At this point,
			it is the user's responsibilty to generate a
			driver for the generated c code.  line.c has been
			provided as a flashy example.  Multilevel logic
			is planned in a future release.
17/10/97	Added more descriptive error messages to ver like so...
			** syntax error near token ';' on line 51.32:
			assign #6 d[3] = (a[3] & (~ b[3;
			                               ^
			Source program has errors.
17/10/97	Added aet generation routines to cyco generated code.
			Look at examples/cla-cycle to see how to use
			this feature.
26/10/97	Started work on an external macro expander for generate
			statements.
27/10/97	Added more functionality to the macro expander/bugfixes.
28/10/97	Added for statements, etc to the macro expander for added
			utility.
05/11/97	Sped up Cyco by adding the -w option which rewrites
			the ivf file to stdio with as many wires optimized
			out as possible.  Cyco speed increase is 6x
			when run on lines-cyco.v.  Also, the resulting
			.c file should be a bit faster since it will 
			have a smaller t[] symbol table and be missing
			many unnecessary assignment statements.
15/11/97	Installed Linux on my pc (got sick of w95) and made Anna
			compatible with Linux.  Also did minor bugfixes
			to Ver (missing args in printf statements that
			worked fine on my NetBSD Amiga box and my 
			Solaris test ones..)
20/12/97	Fixed grammar for ver.y such that wire and assign 
			statements can be interspersed among module
			calls and other gates.  
20/12/97	Added signal directions so "assign k[0:7]=l[7:0];"
			creates a 7-0 crossover rather than
			assigning the signals like k[7]=l[7], etc..
20/12/97	Cleaned up the assign statement grammar so the 
			expression parser from gen could be incorporated
			into ver thus allowing numeric expressions such
			as a[1+2], etc.  Divide by zeros on / and % will
			point out the offending expression then halt
			compilation after the whole program parses.
21/12/97	Further fixed up assignment grammar so the gates that
			are output are maximal width rather than always
			two wide with a n-1 temporaries for an n-bit
			wide gate.  Also added nor (~|), nand (~^), and
			xnor (~^) operators to assign statements.
22/12/97	Relaxed xor() and xnor() to have any arbitrary number
			of inputs greater than or equal to two.
25/12/97	Now allow assign statements inside of gate primitives
			like this: and(o,~a,a^b,a&(b|c)&d,d);
25/12/97	Added concatenation statements to bit vector assignments:
			assign a[0:7]={2{b|c,d&e,f^g,~h}};
			Merry Christmas!
26/12/97	Added 'h 'o 'b 'd format numbers to the repertoire of bit
			vector stuff.  Also complain to user now if zero
			length duplication counts are encountered with the
			{number{ } } concatenation operator.
26/12/97	Redid the expression grammar.  Statements like:
			assign a[3:0]=b[3:0]&c[3:0]; are now possible
			along with hosts of operations involving { }
			with that.
27/12/97	Assign statements can now handle vectors as defined in
			input, output, and wire statements.  What this
			means is a statement like assign o=i; will assign
			*all* of vector i to all of vector o.  Note that
			the direction of the assign goes straight across and
			bits will *not* cross even if defined criss-cross
			in the port or wire statements.
30/12/97	Assign statements will cross properly now--assignment
			direction depends on the direction the bits
			are specified in the input, output, or wire
			statements.  
30/12/97	You can put functions in module instantiations now:
			test mod1(o,a[3:0]^b);  Amazing what you can
			do when there's 14" of snow outside and nothing
			else to do.  =)
31/12/97	Added unary reduction operators to the grammar.
31/12/97	Discovered that you can't do empty module declarations since
			I/O ports were always expected.  Fixed the grammar
			to allow it.
04/01/98	Added drive strengths and gate names to gate specifications.
			Note that this information is simply thrown away
			(information is not saved on a parser reduce op)
			because it has no import to either Cyco or vsim.
			It is just there to facilitate parsing if such
			items do pop up:
			nand (strong0,strong1) #3 gate1(a,b,c), gate2(d,e,f);
04/01/98	Made module names optional as they're not really required in
			Verilog.  Also, you can now stack several module
			instantiations in one statement similar to how one
			would define multiple gates.
04/01/98	Changed macro escape from {stuff} to `stuff` in gen so that 
			concatenation operations in .v files wouldn't
			cause gen to suffer parse errors.
05/01/98	Added array of instances to the module instantiation
			grammar and flattening routines.  See 
			linedraw.v in examples/lines and compare it
			to the one in examples/lines-cycle.  Note how the
			former is much more compact with array 
			instantiations.  (old .v removed in later versions
			-15.01.98 ajb)
06/01/98	Added array of gate instances to gate instantiation.
			Format is same as for array of modules above.
11/01/98	Added tri, wand, wor, etc. statements.  They all function
			as plain vanilla wire statements at this point and 
			timing information isn't used.  That will be used 
			later when those statements are extracted in a
			flatten.  (i.e., the flatten routines have to be
			updated yet.)
11/01/98	Added vectored and scalared keywords to the wire, wand, etc.
			statements and checking for it in the the assignment of 
			expressions and expression parser.
11/01/98	The tri, wire, etc statements function as they are supposed to.
			Delays work, etc.  However, drivestrengths are ignored.
			The gates WIRE, WAND, WOR, TRI0, TRI1, SUPPLY0, SUPPLY1
			have to be added to vsim yet though..Note that delays
			on input ports are unimplemented.
12/01/98	Updated the examples/line-cycle directory such that the .runme
			will build a fully working executable rather than
			making the user intervene.  Looks nice, doesn't it?
13/01/98	Updated vsim and anna to handle 0,1,x,z logic.
14/01/98	Fixed bug where component outputs weren't considered for
			wire, wand, etc. statements.
15/01/98	Updated vsim so it could finally handle $x and $z node
			values and initialize any gates that use those
			values on the 1st simulator step.  Note that for
			the time being, all nodes are initialized to
			'x' on simulator startup.  If you need 'z'
			values on inputs, you'll have to force them in
			vsim for now.
15/01/98	Added supply0, supply1, tri0, tri1, and wire primitives
			to vsim.  Have to add wand and wor yet..
15/01/98	Added wand and wor primitives.  These differ from their
			and/or counterparts as they have the ability to
			pass z values..
15/01/98	Added buf, bufif0, bufif1, notif0, notif1 gates to both
			ver and vsim.  As with the not gate, these all
			have only single outputs.
15/01/98	Added tristate bus example "bus" in the examples
			directory that uses the bufif1 gate.
15/01/98	Added nmos and pmos gates to both ver and vsim.  Also
			added their r versions (rnmos, rpmos).  
			The pull strengths are ignored because the 
			simulator does not model strengths.
15/01/98	Added pullup and pulldown gates to vtokens.l.  They
			return the const1 and const0 tokens to the
			parser.  (OK since strengths are not modelled.)
16/01/98	Added the option of being able to use named ports for
			module instances.  This lets you specify ports
			out of order if you so choose:
			blahmodule(.a(x1), .b(x2), .c(x3)); says that
			x1 goes to port a, x2 to b, etc.
17/01/98	Patched addgate() through the creation of addgate2() so
			multiple output NOT and BUF gates are now 
			possible.  The single input is listed last in
			the argument list.  Note that the if0/if1 versions
			of these gates still have only a single output
			as per the ieee 1364-1995 verilog grammar.
17/01/98	Fixed the grammar rule for latches as the gate port def
			for NOT and BUF was being incorrectly used for
			latches.  (i.e., latches are supposed to have
			only one output.)
20/01/98	Added /* */ format comments (nestable) and the ability to
			embed "_" characters anywhere after the leading
			digit in a 'd 'b 'o 'h number to enhance
			readability.
20/01/98	Added parameter statements (right after module headers).
			Note that parameter values are local to the module
			they are defined in *only* in this implementation.
			There is no defparam statement either.  
			Additionally, using undefined parameters will cause
			a syntax error.  (Defined parameters patch the lexer
			to produce a number rather than identifier token.)
21/01/98	Added ability to have multiple semicolons in a row.
25/01/98	Added two missing component instantion definitions types
			(empty LP RP) to the ver.y grammar.
03/01/98        Added -v flag to ver.  With this, the compiler will output
                        a vhdl translation of your verilog to stdio
                        rather than creating an ivf file.
05/01/98        Signals in portmaps coalesce into bitvectors if possible
                        now.  Also note that the only gates supported are
                        AND, OR, NOT, XOR, NAND, NOR, XNOR, BUF for the
                        time being.  
14/01/98        Fixed cyco for parallel simulation.  Any nonzero values
                        are ~0.  That way, *all* the bits are set rather
                        than just the low order one.
15/01/98        Fixed ver so it doesn't generate __name type component
                        names when it's forced to name an unnamed 
                        component.  Now it's c_name.  Similar scheme
                        for arrays of components...the __ has been
                        replaced with _c_.
10/04/98        Fixed vtokens.l so comments don't throw off error reporting
25/04/98        Updated Cyco so that combinational logic *after* latches
                        gets updated properly.  Did this by splitting up
                        the combinational logic evaluation and the latch
                        assignments.  By doing so, the user has finer
                        control over what gets evaluated and an increase
                        in throughput is possible.